The Spyglass suite of tools uses predictive analysis technique that performs structural analysis on Verilog and VHDL RTL to detect design problems in SoCs and ASICs.
http://www.atrenta.com/
John Cooley's independent newsletter on Synthesis and related silicon design automation software. Originally the e-mail Synopsys Users Group (ESNUG). A compiled set of emails cont...
http://www.deepchip.com/
A merging of design software companies, which creates a complete PC based design environment. This includes everything from ASIC design to PCB design.
http://www.innoveda.com
Tharas Systems, Inc. provides hardware accelerated RTL simulation for SoC, up to 1000x the performance of software based simulators.
http://www.tharas.com
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